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preliminary this is a product that has fixed target specifications but are subject ramtron international corporation to change pending characterization results . 1850 ramtron drive, colorado springs, co 80921 (800) 545 - f ram, (719) 481 - 7000 rev. 1.1 www.ramtron.com may 2011 page 1 of 12 fm 24c 16c 16kb serial 5v f - ram memory features 16k bit ferroelectric nonvolatile ram ? organized as 2,048 x 8 bits ? high endurance (10 12 ) read/write cycles ? 36 year data retention at +75 ? c ? nodelay? writes ? advanced high - reliability ferroelectric process fast two - wire serial interface ? up to 1mhz maximum bus frequency ? direct hardware replacement for eeprom ? supports legacy timing for 100 khz & 400 khz low power operation ? 5v operation ? 1 0 0 ? a active current (100 khz) ? 4 ? a (typ.) sta ndby current industry standard configuration ? industrial temperature - 40 ? c to +85 ? c ? 8 - pin green /rohs soic ( - g) description the fm 24c 16c is a 16 - kilobit nonvolatile memory employing an advanced ferroelectric process. a ferroelectric random access memor y or fram is nonvolatile and performs reads and writes like a ram. it provides reliable data retention for 36 years while eliminating the complexities, overhead, and system level reliability problems caused by eeprom and other nonvolatile memories. t he f m 24c 16c performs write operations at bus speed. no write delays are incurred. data is written to the memory array in the cycle after it has been successfully transferred to the device. the next bus cycle may commence immediately without the need for data p olling. the fm 24c 16c is capable of supporting 10 12 read/write cycles, or a million times more write cycles than eeprom. these capabilities make the fm 24c 16c ideal for nonvolatile memory applications requiring frequent or rapid writes. examples range from data collection where the number of write cycles may be critical, to demanding industrial controls where the long write time of eeprom can cause data loss. the combination of features allows the system to write data more frequently, with less system overhe ad. the fm 24c 16c provides substantial benefits to users of serial eeprom, and these benefits are available as a hardware drop - in replacement. the fm 24c 16c is available in an industry standard 8 - pin soic package and uses a familiar two - wire protocol. the specifications are guaranteed over the ind ustrial temperature range from - 40c to +85c. pin configuration pin names function sda serial data/address scl serial clock wp write protect vss ground vdd supply voltage ordering information fm24 c 16c - g green/rohs 8 green/rohs 8 nc nc nc vss vdd wp scl sda 1 2 3 4 8 7 6 5
FM24C16C - 16kb 5v i2c f - ram rev. 1.1 may 2011 page 2 of 12 figure 1. block diagram pin description pin name type pin description sda i/o serial data address: this is a bi - directional data pin f or the two - wire interface. it employs an open - drain output and is intended to be wire - or?d with other devices on the two - wire bus. the input buffer incorporates a schmitt trigger for noise immunity and the output driver includes slope control for falling e dges. a pull - up resistor is required. scl input serial clock: the serial clock input for the two - wire interface. data is clocked - out on the falling edge and clocked - in on the rising edge. wp input write protect: when wp is high, the entire array is write - protected. when wp is low, all addresses may be written. this pin is internally pulled down. vdd supply supply voltage (5v) vss supply ground nc - no connect address latch ` 256 x 64 fram array data latch 8 sda counter serial to parallel converter control logic scl wp
FM24C16C - 16kb 5v i2c f - ram rev. 1.1 may 2011 page 3 of 12 overview the fm 24c 16c is a serial fram memory. the memory array is logically organized as a 2,048 x 8 memory array and is accessed using an industry standard two - wire interface. functional operation of the fram is similar to serial eeproms. the major difference between the fm 24c 16c and a serial eeprom with the same pinout relates to its superior write performance. memory architecture when accessing the fm 24c 16c , the user addresses 2,048 locations each with 8 data bits. these data bits are shifted serially. the 2,048 addresses are accessed using the two - wire protocol, which includes a slave addre ss (to distinguish from other non - memory devices), a row address, and a segment address. the row address consists of 8 - bits that specify one of 256 rows. the 3 - bit segment address specifies one of 8 segments within each row. the complete 11 - bit address spe cifies each byte uniquely. most functions of the fm 24c 16c either are controlled by the two - wire interface or handled automatically by on - board circuitry. the memory is read or written at the speed of the two - wire bus. unlike an eeprom, it is not necessar y to poll the device for a ready condition since writes occur at bus speed. that is, by the time a new bus transaction can be shifted into the part, a write operation is complete. this is explained in more detail in the interface section below. note that the fm 24c 16c contains no power management circuits other than a simple internal power - on reset. it is the user?s responsibility to ensure that vdd is within data sheet tolerances to prevent incorrect operation. two - wire interface the fm 24c 16c employs a bi - directional two - wire bus protocol using few pins and little board space. figure 2 illustrates a typical system configuration using the fm 24c 16c in a microcontroller - based system. the industry standard two - wire bus is familiar to many users but is descri bed in this section. by convention, any device that is sending data onto the bus is the transmitter while the target device for this data is the receiver. the device that is controlling the bus is the master. the master is responsible for generating the c lock signal for all operations. any device on the bus that is being controlled is a slave. the fm 24c 16c is always a slave device. the bus protocol is controlled by transition states in the sda and scl signals. there are four conditions including start, s top, data bit, and acknowledge. figure 3 illustrates the signal conditions that define the four states. detailed timing diagrams are shown in the electrical s pecifications section . figure 2. typical system configuration microcontroller sda scl fm 24 c 16 c sda scl other non - memory slave device vdd r min = 1 . 8 k ohm r max = t r / c bus
FM24C16C - 16kb 5v i2c f - ram rev. 1.1 may 2011 page 4 of 12 figure 3. data transfer protocol stop condition a stop condition is indicated when the bus master drives sda from low to high while the scl signal is high. all operations using the fm 24c 16c must end with a stop condition. if an operation is pending when a stop is asserted, the operation will be aborted. the master must have control of sda (not a memory read) in order to assert a stop condition. start condition a start condition is indicated when the bus master drives sda from high to low while the scl signal is high. all read and write transactions begin with a start condition. an operation in progress can be aborted by asserting a start condition at any time. aborting an operation using the start condition will prepare th e fm 24c 16c for a new operation. if during operation the power supply drops below the specified vdd minimum, the system should issue a start condition prior to performing another operation. data/address transfer all data transfers (including addresses) t ake place while the scl signal is high. except under the two conditions described above, the sda signal should not change while scl is high. for system design considerations, keeping scl in a low state while idle improves robustness. acknowledge the acknow ledge takes place after the 8 th data bit has been transferred in any transaction. during this state, the transmitter should release the sda bus to allow the receiver to drive it. the receiver drives the sda signal low to acknowledge receipt of the byte. if the receiver does not drive sda low, the condition is a no - acknowledge and the operation is aborted. the receiver would fail to acknowledge for two distinct reasons. first is that a byte transfer fails. in this case, the no - acknowledge ends the current operation so that the part can be addressed again. this allows the last byte to be recovered in the event of a communication error. second and most common, the receiver does not acknowledge to deliberately end an operation. for example, during a read ope ration, the fm 24c 16c will continue to place data onto the bus as long as the receiver sends acknowledges (and clocks). when a read operation is complete and no more data is needed, the receiver must not acknowledge the last byte. if the receiver acknowledg es the last byte, this will cause the fm 24c 16c to attempt to drive the bus on the next clock while the master is sending a new command such as a stop. slave address the first byte that the fm 24c 16c expects after a start condition is the slave address. as shown in figure 4, the slave address contains the device type, the page of memory to be accessed, and a bit that specifies if the transaction is a read or a write. bits 7 - 4 are the device type and should be set to 1010b for the fm 24c 16c . the device type allows other types of functions to reside on the 2 - wire bus within an identical address range. bits 3 - 1 are the page select. they specify the 256 - byte block of memory that is targeted for the current operation. bit 0 is the read/write bit. a 0 indicates a write operation. stop (master) start (master) 7 data bits (transmitter) 6 0 data bit (transmitter) acknowledge (receiver) scl sda
FM24C16C - 16kb 5v i2c f - ram rev. 1.1 may 2011 page 5 of 12 figure 4. slave address word address after the fm 24c 16c (as receiver) acknowledges the slave id, the master will place the word address on the bus for a write operation. the word address is the lower 8 - bits of the address to be combined with the 3 - bits of the page select to specify the exact byte to be written. the complete 11 - bit address is latched internally. no word address occurs for a read operation, though the 3 - bit page select is latched internally. reads always use the lower 8 - bits that are held internally in the address latch. that is, reads always begin at the address following the previous access. a random read address can be loaded by doing a write operation as explained below. after transmiss ion of each data byte, just prior to the acknowledge, the fm 24c 16c increments the internal address latch. this allows the next sequential byte to be accessed with no additional addressing. after the last address (7ffh) is reached, the address latch will ro ll over to 000h. there is no limit on the number of bytes that can be accessed with a single read or write operation. data transfer after all address information has been transmitted, data transfer between the bus master and the fm 24c 16c can begin. for a read operation the device will place 8 data bits on the bus then wait for an acknowledge. if the acknowledge occurs, the next sequential byte will be transferred. if the acknowledge is not sent, the read operation is concluded. for a write operation, the f m 24c 16c will accept 8 data bits from the master then send an acknowledge. all data transfer occurs msb (most significant bit) first. memory operation the fm 24c 16c is designed to operate in a manner very similar to other 2 - wire interface memory products. the major differences result from the higher performance write capability of fram technology. these improvements result in some differences between the fm 24c 16c and a similar configuration eeprom during writes. the complete operation for both writes and re ads is explained below. write operation all writes begin with a slave id then a word address as previously mentioned. the bus master indicates a write operation by setting the lsb of the slave address to a 0. after addressing, the bus master sends each by te of data to the memory and the memory generates an acknowledge condition. any number of sequential bytes may be written. if the end of the address range is reached internally, the address counter will wrap from 7ffh to 000h. unlike other nonvolatile me mory technologies, there is no write delay with fram. the entire memory cycle occurs in less time than a single bus clock. therefore, any operation including read or write can occur immediately following a write. acknowledge polling, a technique used with eeproms to determine if a write is complete is unnecessary and will always return a ?ready? condition. an actual memory array write occurs after the 8 th data bit is transferred. it will be complete before the acknowledge is sent. therefore, if the user desires to abort a write without altering the memory contents, this should be done using start or stop condition prior to the 8 th data bit. the fm 24c 16c needs no page buffering. the memory array can be write protected using the wp pin. setting the wp pin to a high condition (vdd) will write - protect all addresses. the fm 24c 16c will not acknowledge data bytes that are written to protected addresses. in addition, the address counter will not increment if writes are attempted to these addresses. setting wp to a low state (vss) will deactivate this feature. figure 5 and 6 below illustrate both a sing le - byte and multiple - byte write cases . 1 0 1 0 a2 a1 a0 r/w slave id page select
FM24C16C - 16kb 5v i2c f - ram rev. 1.1 may 2011 page 6 of 12 figure 5. single byte write figure 6. multiple byte write read operation there are two types of read operations. they are current address read and selective address read. in a current address read, the fm 24c 16c uses the internal address latch to supply the lower 8 address bits. in a selective read, the user per forms a procedure to set these lower address bits to a specific value. current address & sequential read as mentioned above the fm 24c 16c uses an internal latch to supply the lower 8 address bits for a read operation. a current address read uses the exist ing value in the address latch as a starting place for the read operation. this is the address immediately following that of the last operation. to perform a current address read, the bus master supplies a slave address with the lsb set to 1. this indica tes that a read operation is requested. the 3 page select bits in the slave id specify the block of memory that is used for the read operation. on the next clock, the fm 24c 16c will begin shifting out data from the current address. the current address is th e 3 bits from the slave id combined with the 8 bits that were in the internal address latch. beginning with the current address, the bus master can read any number of bytes. thus, a sequential read is simply a current address read with multiple byte tran sfers. after each byte, the internal address counter will be incremented. each time the bus master acknowledges a byte this indicates that the fm 24c 16c should read out the next sequential byte. there are four ways to properly terminate a read operation. f ailing to properly terminate the read will most likely create a bus contention as the fm 24c 16c attempts to read out additional data onto the bus. the four valid methods are as follows. 1. the bus master issues a no - acknowledge in the 9 th clock cycle and a s top in the 10 th clock cycle. this is illustrated in the diagrams below. this is the preferred method. 2. the bus master issues a no - acknowledge in the 9 th clock cycle and a start in the 10 th . 3. the bus master issues a stop in the 9 th clock cycle. bus contenti on may result. 4. the bus master issues a start in the 9 th clock cycle. bus contention may result. if the internal address reaches 7ffh it will wrap around to 000h on the next read cycle. figures 7 and 8 show the proper operation for current address reads. selective (random) read a simple technique allows a user to select a random address location as the starting point for a read operation. it uses the first two bytes of a write operation to set the internal address byte followed by subsequent read operatio ns. to perform a selective read, the bus master sends out the slave address with the lsb set to 0. this specifies a write operation. according to the write protocol, the bus master then sends the word address byte that is loaded into the internal address latch. after the fm 24c 16c acknowledges the word address, the bus master issues a start condition. this simultaneously aborts the write operation and allows the read command to be issued with the slave address set to 1. the operation is now a current addre ss read. this operat ion is illustrated in figure 9. s a slave address 0 word address a data byte a p by master by f - ram start address & data stop acknowledge s a slave address 0 word address a data byte a p by master by f - ram start address & data stop acknowledge data byte a
ramtron FM24C16C - 16kb 5v i2c f - ram rev. 1.1 may 2011 page 7 of 12 figure 7. current address read figure 8. sequential read figure 9. selective (random) read endurance the f m 24c 16c internally operates with a read and restore mechanism. therefore, endurance cycles are applied for each read or write cycle. the memory architecture is based on an array of rows and columns. each read or write access causes an endurance cycle for a n entire row. in the fm24c 16c , a row is 64 bits wide. every 8 - byte boundary marks the beginning of a new row. endurance can be optimized by ensuring frequently accessed data is located in different rows . regardless, fram read and write endurance is effect ively unlimited at the 1mhz two - wire speed. even at 3000 accesses per second to the same row, 10 years time will elapse before 1 trillion endurance cycles occur. s a slave address 1 data byte 1 p by master by f - ram start address stop acknowledge no acknowledge data s a slave address 1 data byte 1 p by master by f - ram start address stop acknowledge no acknowledge data data byte a acknowledge s a slave address 1 data byte 1 p by master by f - ram start address stop no acknowledge data data byte a acknowledge s a slave address 0 word address a start address acknowledge
FM24C16C - 16kb 5v i2c f - ram rev. 1.1 may 2011 page 8 of 12 electrical specifications absolute maximum ratings symbol description ratings v dd power supply voltage with respect to v ss - 1.0v to +7.0v v in voltage on any signal pin with respect to v ss - 1.0v to +7.0v and v in < v dd +1.0v * t stg storage temperature - 55 ? c to +125 ? c t lead lead temperature (soldering, 10 seconds) 26 0 ? c v esd electrostatic discharge voltage - human body model (aec - q100 - 002 rev. e) - charged device model (aec - q100 - 011 rev. b) - machine model ( a ec - q100 - 003 rev. e ) 2.5kv 1.25kv 100v package moisture sensitivity level msl - 1 * exception: the v in < v dd +1.0v restricti on does not apply to the scl and sda inputs. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only, and the functional operation of the device at these or any other conditions abov e those listed in the operational section of this specification is not implied. exposure to absolute maximum ratings conditions for extended periods may affect device reliability. dc operating conditions (t a = - 40 ? c to + 85 ? c, v dd = 4.5v to 5.5v unless otherwise specified) symbol parameter min typ max units notes v dd main power supply 4.5 5.0 5.5 v i dd vdd supply current @ scl = 100 khz @ scl = 400 khz @ scl = 1 mhz 100 200 400 ? a ? a ? a 1 i sb standby current 4 10 ? a 2 i li input leakage curre nt 1 ? a 3 i lo output leakage current 1 ? a 3 v il input low voltage - 0.3 0.3 v dd v v ih input high voltage 0.7 v dd v dd + 0.3 v v ol output low voltage @ i ol = 3 ma 0.4 v r in input resistance (wp pin) for v in = v il (max) for v in = v ih (min ) 4 0 1 k ? m ? 5 v hys input hysteresis 0.05 v dd v 4 notes 1. scl toggling between v dd - 0.3v and v ss , other inputs v ss or v dd - 0.3v. 2. scl = sda = v dd . all inputs v ss or v dd . stop command issued. 3. v in or v out = v ss to v dd . does not apply to wp pin . 4. this par ameter is characterized but not tested. 5. the input pull - down circuit is strong ( 4 0k ? ) when the input voltage is below v il and much weaker (1m ? ) when the input voltage is above v ih .
FM24C16C - 16kb 5v i2c f - ram rev. 1.1 may 2011 page 9 of 12 a c parameters (t a = - 40 ? c to + 85 ? c, v dd = 4.5v to 5.5v unless otherwis e specified) symbol parameter min max min max min max units notes f scl scl clock frequency 0 100 0 400 0 1000 khz 1 t low clock low period 4.7 1.3 0.6 ? s t high clock high period 4.0 0.6 0.4 ? s t aa scl low to sda data out valid 3 0.9 0.55 ? s t buf bus free before new transmission 4.7 1.3 0.5 ? s t hd:sta start condition hold time 4.0 0.6 0.25 ? s t su:sta start condition setup for repeated start 4.7 0.6 0.25 ? s t hd:dat data in hold time 0 0 0 ns t su:dat data in setup time 250 100 100 ns t r input rise time 1000 300 300 ns 2 t f input fall time 300 300 100 ns 2 t su:sto stop condition setup 4.0 0.6 0.25 ? s t dh data output hold (from scl @ v il ) 0 0 0 ns t sp noise suppression time constant on scl, sda 50 50 50 ns notes : all scl specifications as well as start and stop conditions apply to both read and write operations. 1 the speed - related specifications are guaranteed characteristic points from dc to 1 mhz. 2 this parameter is periodically sampled and not 1 00% tested. capacitance ( t a = 25 ? c, f=1.0 mhz, v dd = 5v) symbol parameter max units notes c i/o input/ output c apacitance (sda) 8 pf 1 c in input c apacitance 6 pf 1 notes 1 this parameter is periodically sampled and not 100% tested. power cycle timing power cycle timing ( t a = - 40 ? c to +85 ? c , v dd = 4.5v to 5.5v unless otherwise specified ) symbol parameter min max units notes t pu power up (v dd min) to first access (start condition) 1 - ms t pd last access (stop condition) t o power down (v dd min) 0 - ? s t vr v dd rise time 30 - ? s/v 1 t vf v dd fall time 10 0 - ? s/v 1 notes 1. sl ope measured at any point on v dd waveform . v d d m i n . v d d s d a , s c l t v r t p d t p u t v f
FM24C16C - 16kb 5v i2c f - ram rev. 1.1 may 2011 page 10 of 12 ac test conditions equivalent ac load circuit input pulse levels 0.1 v dd to 0.9 v dd input rise and fall times 10 ns input and output timing levels 0.5 v dd diagram notes all start and stop timing parameters apply to both read and write cycles. clock specifications are identical for read and write cycles. write timing parameters apply to slave address, word address, and write data bits. functional relationships are illustrated in the relevant data sheet sections. these diagrams illustrate the timing parameters only. read bus timing write bus timing data retention symbol parameter min max units notes t dr @ +85oc 10 - years @ +80oc 18 - years @ +75oc 36 - years t su:sda start t r t f stop start t buf t high 1/fscl t low t sp t sp acknowledge t hd:dat t su:d at t aa t dh scl sda t su:sto start stop start acknowledge t aa t hd:dat t hd:sta t su:dat scl sda 5.5v output 1700 ? 100 pf
FM24C16C - 16kb 5v i2c f - ram rev. 1.1 may 2011 page 11 of 12 mechanical drawing 8 - pin soic (jedec standard ms - 012 variation aa) refer to jedec ms - 012 for complete dimensions and notes. all dimensions in millimeters . soic package marking scheme legend: xxx xx x= part number, p= package type r=rev code, lllllll= lot code ric=ramtron int?l corp, yy=year, ww=work week example: fm 24c 1 6c , green soic package, year 2010, work week 49 fm 24c 16c - g a 00002g1 ric1049 xxxx xxx - p r ll llll l ricyyww p i n 1 3 . 9 0 0 . 1 0 6 . 0 0 0 . 2 0 4 . 9 0 0 . 1 0 0 . 1 0 0 . 2 5 1 . 3 5 1 . 7 5 0 . 3 3 0 . 5 1 1 . 2 7 0 . 1 0 m m 0 . 2 5 0 . 5 0 4 5 0 . 4 0 1 . 2 7 0 . 1 9 0 . 2 5 0 - 8 r e c o m m e n d e d p c b f o o t p r i n t 7 . 7 0 0 . 6 5 1 . 2 7 2 . 0 0 3 . 7 0
FM24C16C - 16kb 5v i2c f - ram rev. 1.1 may 2011 page 12 of 12 revision history revision date summary 1.0 3/22/2011 initial release 1.1 5/ 2 0 /2011 added esd ratings.

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